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1 Mbit SPI Serial Flash
A Microchip Technology Company
SST25VF010A
Data Sheet
6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable
(WREN) instruction must be executed.
7. Block addresses for: use A MS -A 15 , remaining addresses can be V IL or V IH
8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,
followed by the data to be programmed.
9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in
conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR
instruction to make both instructions effective.
11. Manufacturer’s ID is read with A 0 =0, and Device ID is read with A 0 =1. All other address bits are 00H. The Manufac-
turer’s and Device ID output stream is continuous until terminated by a low to high transition on CE#
12. Device ID = 49H for SST25VF010A
Read (20 MHz)
The Read instruction outputs the data starting from the specified address location. The data output
stream is continuous through all addresses until terminated by a low to high transition on CE#. The
internal address pointer will automatically increment until the highest memory address is reached.
Once the highest memory address is reached, the address pointer will automatically increment to the
beginning (wrap-around) of the address space, i.e. for 4 Mbit density, once the data from address loca-
tion 7FFFFH had been read, the next output will be from address location 00000H.
The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A 23 -
A 0 ]. CE# must remain active low for the duration of the Read cycle. See Figure 4 for the Read
sequence.
CE#
MODE 3
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47
48
55 56
63 64
70
SCK
MODE 0
SI
03
ADD.
ADD.
ADD.
SO
MSB
MSB
HIGH IMPEDANCE
N
D OUT
N+1
D OUT
N+2
D OUT
N+3
D OUT
N+4
D OUT
MSB
1265 F04.0
Figure 4: Read Sequence
?2011 Silicon Storage Technology, Inc.
10
S725081A
10/11
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